Cyclic redundancy check (CRC) codes are often used to detect errors in a block of transmitted bits. In general, an N bit CRC code will have a probability of failure of (½)N which occurs in a very high noise environment. Values of 8, 16 and 32 are common for N. A failure is defined as the code check passing when there are errors in the message. A second failure mode exists when there are no errors in the message but the CRC check fails, signifying that one or more of the CRC bits were in error. This mechanism occurs much less frequently and the associated cost of discarding a good message is small.
Modern data networking communication systems are relying more and more on burst transmissions to perform network command and control functions as well as the transmission of burst data. Since, it is standard practice in industry to use a CRC code for error detection, each packet or burst of data includes a CRC code with its data. This allows the receiver to determine with fairly high accuracy if the received bits are correct. The disadvantage of this technique, however, is that it adds overhead to the transmission by requiring the transmission of extra bits. The CRC bits that are appended to the data message to send over the air can be calculated in a number of different ways but often rely on feedback shift-register architectures, where all the bits of the entire message to be encoded are passed through the shift-register. The CRC bits are the state of the shift-registers at the conclusion of the process. Standard sizes for CRC codes used in industry are 32, 16 and 8 bits. For short burst transmissions these may end up being a significant portion of a transmission.
As noted above, cyclic redundancy check (CRC) codes are commonly used in many packetized data transmissions to provide error detection. The CRC is an additional 8, 16 or 32 bits that are sent along with the packetized data. A receiver recalculates the CRC and checks it against the received CRC to determine if the received packet is error free.
As the data rates increases, however, the time allowed to implement the CRC processing decreases, which creates loading and latency issues in the system. It would be advantageous if an alternative fast error detection (FED) mechanism with a performance similar to a standard CRC could be provided which can be implemented in a computationally efficient form suited for digital signal processor (DSP) technology often used in modern radios, for example, software defined radios and/or cognitive radio systems.